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Currently when any of speed_mode, part, or dev fails to be parse as a number, no error is reported. In this case __init_mmc_device() is called with weird arguments, probably zeroes if there's no digit prefixing the argument, which is especially confusing when the invocation occasionally succeeds. Let's check whether arguments are valid numbers without trailing characters. This is quite helpful for speed_mode: it requires an index instead of a mode name, one may easily pass in a string, which will be parsed as zero (MMC_LEGACY), without carefully reading the documentation, then finds the MMC device is under an unexpected mode. Signed-off-by: Yao Zi <me@ziyao.cc> Tested-by: Anshul Dalal <anshuld@ti.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Return symbolic value CMD_RET_FAILURE instead of literal "1" when failing to switch the partition to improve readability. Signed-off-by: Yao Zi <me@ziyao.cc> Tested-by: Anshul Dalal <anshuld@ti.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
My Linaro email address is no longer valid. Update entries in the MAINTAINERS file, and add a mapping in the mailmap file. Signed-off-by: Sughosh Ganu <sughosh.ganu@arm.com>
…odians/u-boot-mmc - Add DMA support for mediatek mmc - Cleanup mmc cmd - Fix typos in mmc [trini: Fix "quoted string split across lines" checkpatch warning] Signed-off-by: Tom Rini <trini@konsulko.com>
Excessive default value causes crash on hardware: x86 baytrail E3845 It is unclear where the data is being populated being 'BLOBLISTT_TCPA_LOG' is not found elsewhere in the u-boot tree. This leads to confusion about how much space for TPM log is actually needed. This was tested on hardware using TPMv1. Signed-off-by: Eric Schikschneit <eric.schikschneit@novatechautomation.com>
Mediatek MT7620 u-boot does not have PINCONF implementation. Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
Allow the system to reset the CPU without calling the reset controller. This patch also removed the default SYSRESET controller for MT7628, as it is now optional. Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
The else if branch uses the is_zimage boolean which is initialized to 0 and never set before being tested here. remove the test on is_zimage to make this code reachable. Signed-off-by: Guillaume Ranquet <ranquet.guillaume@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
When compiled with FTRACE=1 U-boot will crash as %rdi is clobbered in board_init_f_alloc_reserve() and board_init_f_init_reserve() will memset the .text segment instead of the global_data struct. According to the System V AMD64 ABI %rdi is not preserved and the existing code only worked as board_init_f_alloc_reserve() was small enough to not use %rdi. Fix that by always passing the correct argument to board_init_f_init_reserve(). TEST=Can boot on qemu-q35 with FTRACE=1 enabled during build. Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Remove 'complete' member from struct sunxi_nfc The 'complete' member isn't part of the structure, let's remove it. Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Richard Genoud <richard.genoud@bootlin.com> Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Fix pointer from interget warning when compiling for ARM64 When compiling for arm64, we get this error: error: passing argument 2 of ‘__memcpy_fromio’ makes pointer from integer without a cast [-Wint-conversion] Moreover the copy should be made with dedicated readl(), like for any register access on this peripheral, since they are 32bit wide. So, instead of memcpy_fromio(), just use a readl() loop. Introduce nand_readlcpy() to implement this loop. Fixes: 6ddbb1e ("spl: nand: sunxi: use PIO instead of DMA") Suggested-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Richard Genoud <richard.genoud@bootlin.com> Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Harmonize registers definition in sunxi_nand{,_spl}.c files
This is a first step to then include the same file from both
sunxi_nand{,_spl}.c files
Unused defines are also removed
Signed-off-by: Richard Genoud <richard.genoud@bootlin.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
…nand.h Remove unneeded definitions NFC_CMD_R* in sunxi_nand_spl.c No need to define NFC_CMD_RNDOUTSTART, NFC_CMD_RNDOUT and NFC_CMD_READSTART here since they are already in linux/mtd/rawnand.h Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Richard Genoud <richard.genoud@bootlin.com> Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
The sunxi_ccm_reg is legacy, drop its usage from nand related code
For that, CCU_NAND0_CLK_CFG and CCU_AHB_GATE1 are added to the clock
files when missing.
And clock code in sunxi_nand{,_spl}.c and board.c are changed to use the
new scheme.
Moreover, drop AHB_DIV_1 in favor of the more readable CCM_NAND_CTRL_M/N
Suggested-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Richard Genoud <richard.genoud@bootlin.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Merge common register definitions from sunxi_nand{,_spl}.c
The Allwinner NAND controller registers where in both files, so let's
just merge all that in a header, it will be easier for maintenance.
NB: the defines are also harmonized with Linux driver
No functional change
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Richard Genoud <richard.genoud@bootlin.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Introduce per SoC capabilities in sunxi_nand.c This prepares for the H616 support that has quite a lot differences in registers offset and capabilities. Start with the ECC strength table. No functional change. Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Richard Genoud <richard.genoud@bootlin.com> Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
ECC_ERR_CNT register offset moved in H616, so let's make it a SoC cap Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Richard Genoud <richard.genoud@bootlin.com> Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
USER_DATA register offset moved in H616, so let's make it a SoC cap Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Richard Genoud <richard.genoud@bootlin.com> Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Move ECC_PAT_FOUND register in SoC capabilities structure This register offset moved in H616, it's now its own register (@0x3c, bits 0-31), not shared with NFC_ECC_ST any more (was @0x38 bits 16-31). Push that specificity in caps structure. Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Richard Genoud <richard.genoud@bootlin.com> Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Introduce has_ecc_block_512 capability The H616 controller can't handle 512 bytes ECC block size. The NFC_ECC_BLOCK_512 bit disappeared in H6, and NDFC_RANDOM_EN took its place. So, add has_ecc_block_512 capability to only set this bit on SoC having it. On the way, let's drop NFC_ECC_BLOCK_SIZE_MSK which was just a mask for the very same bit. No functional change. Signed-off-by: Richard Genoud <richard.genoud@bootlin.com> Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
NFC_ECC_MODE register offset moved in H616, so let's make it a SoC cap No functional change. Signed-off-by: Richard Genoud <richard.genoud@bootlin.com> Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Introduce NDFC Pattern ID Register in capability structure The H6/H616 pattern ID register is not at the same offset as the A10/A23 one, so move its offset into sunxi_nfc_caps. No functional change. Signed-off-by: Richard Genoud <richard.genoud@bootlin.com> Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Introduce per SoC capabilities in sunxi_nand_spl.c Prepare for the H616 support that has quite a lot of differences in registers offset and capabilities. Start with the 512 bytes ECC capability. No functional change. Signed-off-by: Richard Genoud <richard.genoud@bootlin.com> Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
NFC_RANDOM_{EN,DIRECTION} registers offset moved in H616
Let's make it a SoC capability.
NFC_RANDOM_DIRECTION also moved, but it's unused, just remove it.
No functional change.
Signed-off-by: Richard Genoud <richard.genoud@bootlin.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Introduce NDFC Spare Area Register offset in SoC capabilities The H6/H616 spare area register is not at the same offset as the A10/A23 one, so move its offset into sunxi_nfc_caps. No functional change. Signed-off-by: Richard Genoud <richard.genoud@bootlin.com> Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Use defines instead of hardcoded values for NFC_ECC_{ERR_MSK,PAT_FOUND}
SPL is using hard coded values for ECC error detection and empty chunk
detection.
The H6/H616 registers for that have changed, the pattern found is no
more in the NFC_REG_ECC_ST register.
So, don't presume anymore that pattern_found is in NFC_REG_ECC_ST, and
read the pattern_found register to get this information.
Apart from an additional register reading, no functional change.
Signed-off-by: Richard Genoud <richard.genoud@bootlin.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Increase max_oobsize to take into account bigger OOB on 2KiB pages Some NAND chip (e.g. Kioxia TC58NVG1S3HTA00) have a 2KiB page size + 128 bytes OOB. In order to detect them, the max_oobsize has to be increased from 64 to 128 bytes. Tested on Kioxia TC58NVG1S3HTA00 NAND chip on Whatsminer H616 board. Signed-off-by: Richard Genoud <richard.genoud@bootlin.com> Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Use generic macros for ECC_MODE and RANDOM_SEED As H6/H616 registers are different, use more generic macros than hard coded values specific to A10-like SoC. No functional changes. Signed-off-by: Richard Genoud <richard.genoud@bootlin.com> Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Add missing NAND controller-related clock registers
The NAND controller on H6/H616 uses one clock for its internal logic
(NAND0_CLK) and one clock for ECC engine (NAND1_CLK) in addition to AHB
and MBUS clocks.
As NAND{0,1}_CLKs and MBUS_GATE are missing, add them.
The bit locations are from H616/H6 User Manual.
Signed-off-by: Richard Genoud <richard.genoud@bootlin.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Add MBUS Master Clock Gating Register for H6 and H616 For H6/H616, the NAND controller needs the MBUS NAND clock along with CLK_NAND0/1 and CLK_BUS_NAND. The bit locations are from H6/H616 User Manuals. Signed-off-by: Richard Genoud <richard.genoud@bootlin.com> Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Add cmd_stm32key support for STM32MP21x SoCs family. Signed-off-by: Yann Gautier <yann.gautier@foss.st.com> Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
STM32MP21 application processors (STM32 MPUs) based on a single Arm Cortex®-A35 core running up to 1.5 GHz and Cortex®-M33 core running at 300 MHz. It is pin-compatible with the STM32MP2 series in the VFBGA361 10×10 mm package: the STM32MP21 uses a subset of the STM32MP23 pinout, which itself is a subset of the STM32MP25. More details available here : https://www.st.com/en/microcontrollers-microprocessors/stm32mp2-series.html Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Add U-Boot specific file for stm32mp215f-dk board Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Add temporarily bootph-all property in usart2 and syscfg nodes to allows stm32mp215f-dk board to boot. When DT kernel series [1] will be merged and synchronized in U-Boot this patch will be reverted. [1] https://lore.kernel.org/linux-arm-kernel/20260203-upstream_uboot_properties-v6-0-0a2280e84d31@foss.st.com/ Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Same code is duplicated into stm32mp25x.c, stm32mp23x.c and stm32mp21x.c. Migrate read_deviceid(), get_cpu_dev(), get_cpu_rev(), get_cpu_type() and get_cpu_package() into new stm32mp2x.c. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
syscon_get_first_range()'s return value is used as base address to perform a read, without any checks. In case stmp32mp_syscon is not binded, syscon_get_first_range() returns -ENODEV which leads to a "Synchronous abort". Add syscon_get_first_range() check on return value. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
syscon_get_first_range()'s return value is used as base address to perform a read, without any checks. In case stmp32mp_syscon is not binded, syscon_get_first_range() returns -ENODEV which leads to a "Synchronous abort". Add syscon_get_first_range() check on return value. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Update stm32key to support stm32mp21 OTP mapping.
Create a new list of key to support the following differences :
- STM32MP21x SoC support 128b and 25b FSBL encryption keys.
- OEM-KEY1 and OEM-KEY2 used for authentication are in different OTP
from STM32MP25 and STM32MP23.
stm32key is compatible with platform STM32MP2 (aarch64)
Hence, use unsigned long to handle argument addr of function
read_key_value() instead of u32.
Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Add support of OTP key format 2 used by OP-TEE. Key formats are describes in the STM32MPUs references manuals section OTP mapping. Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com> Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Add support of RPROC-FW-KEY for STM32MP25, STM32MP23 and STM32MP21. Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com> Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Add support of RPROC-FW-PKH for STM32MP25, STM32MP23 and STM32MP21. Signed-off-by: Gwenael Treuveur <gwenael.treuveur@foss.st.com> Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Add support of ADAC-PKH for STM32MP21. Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com> Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Enable CONFIG_CMD_STM32KEY flag to enable usage of command stm32key. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
…bled If the CID filtering is enabled, the semaphore mode is disabled as well. To avoid an incorrect behavior and error trace, add a check of CID filtering state before acquiring the semaphore. Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Peripheral holding CID0 cannot be accessed, remove this completely incorrect check. While there, fix and simplify the semaphore checking that should be performed when the CID filtering is enabled. Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Secure state must be checked before handling semaphores, otherwise it can cause an IAC. Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
The variant enum is used to uniquely identify which SoC the PHY block belongs to. It is initially set in the match table, along with the compatible string, it gets copied to driver data struct during probe. SoC specific functions must only be called if the respective variant enum is set. Add switch-case blocks wherever required. Reviewed-by: Mattijs Korpershoek <mkorpershoek@kernel.org> Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
The USB PHY used by the Exynos7870 SoC has a single USB 2.0 interface. Add its dedicated variant enum, compatible, and init/exit functions. The PHY enable bit of Exynos7870's PHY is different in contrast to that of Exynos850 and most Exynos PHYs. To allow this change, a simple if condition is added in exynos_usbdrd_phy_isol() which changes the bitmask. Since the variant enum is required, the function argument is changed to accept the driver data itself. Reviewed-by: Mattijs Korpershoek <mkorpershoek@kernel.org> Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
…ubpartitions Some distributions tend to provide a single combined image with EFS and the system root filesystem. Flashing it as-is in a single partition (usually done in userdata partition as it is the largest) is not bootable as U-Boot does not understand subpartitions. Use blkmap to map the userdata partition into its own block device. Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Add support for EFI capsule updates via U-Boot's DFU. This flashes the boot partition with the new image provided in the capsule. Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Add a default fallback device tree in order to allow a successful build without mentioning the DEVICE_TREE= make flag. Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
…stodians/u-boot-stm STM32 update: _ Add STM32MP21 support (board, machine, cmd_stm32key, cmd_stboard, rifsc) _ pinctrl: stm32 : various update _ stm32prog: clean stm32prog_data struct _ stm32mp2: Fix array bound check in setup_boot_mode() _ stm32mp2: Update dynamically DDR size in MMU table _ rifsc: various fixes
…oot-samsung - Assorted platform and video driver updates
SCMI base protocol device does not have a device tree, it should use and need to use the agent base channel. For scmi_base.[x], there is no real device tree node for it. ofnode_null() is assigned as the device tree node for scmi base protocol device: commit 7eb4eb5 ("firmware: scmi: install base protocol to SCMI agent") However with recent update in commit 0535e46 ("scripts/dtc: Update to upstream version v1.7.2-35-g52f07dcca47c"), SPL panic in fdt_check_node_offset_()->fdt_next_tag(), because offset is -1 and SPL_OF_LIBFDT_ASSUME_MASK is 0xFF. So add a check in x_get_channel() to validate the protocol devices' ofnode. Reported-by: Ye Li <ye.li@nxp.com> Closes: https://lore.kernel.org/u-boot/939a9696-27fa-45a1-b428-feffe21ac6d5@oss.nxp.com/ Signed-off-by: Peng Fan <peng.fan@nxp.com>
Similar to pinctrl_select_state(), add dev_has_ofnode() check before doing the real work. Device(scmi_base.0) does not have a real device node, ofnode_null() is assigned as the device tree node for scmi base protocol device: 'commit 7eb4eb5 ("firmware: scmi: install base protocol to SCMI agent")' However with recent update in 'commit 0535e46 ("scripts/dtc: Update to upstream version v1.7.2-35-g52f07dcca47c")', SPL panic in fdt_check_node_offset_()->fdt_next_tag(), because offset is -1 and SPL_OF_LIBFDT_ASSUME_MASK is 0xFF. So need to validate device tree node. Reported-by: Ye Li <ye.li@nxp.com> Closes: https://lore.kernel.org/u-boot/939a9696-27fa-45a1-b428-feffe21ac6d5@oss.nxp.com/ Signed-off-by: Peng Fan <peng.fan@nxp.com>
Similar to pinctrl_select_state(), add dev_has_ofnode() check before doing the real work. Device(scmi_base.0) does not have a real device node, ofnode_null() is assigned as the device tree node for scmi base protocol device: 'commit 7eb4eb5 ("firmware: scmi: install base protocol to SCMI agent")' However with recent update in 'commit 0535e46 ("scripts/dtc: Update to upstream version v1.7.2-35-g52f07dcca47c")', SPL panic in fdt_check_node_offset_()->fdt_next_tag(), because offset is -1 and SPL_OF_LIBFDT_ASSUME_MASK is 0xFF. So need to validate device tree node. Reported-by: Ye Li <ye.li@nxp.com> Closes: https://lore.kernel.org/u-boot/939a9696-27fa-45a1-b428-feffe21ac6d5@oss.nxp.com/ Signed-off-by: Peng Fan <peng.fan@nxp.com>
…t/custodians/u-boot-fsl-qoriq For SCMI, Power Domain and IOMMU, validate device tree node before continuing, to avoid boot failure.
With the change to regularize the usage of TEST_PY_TEST_SPEC in the sjg-lab stanza with commit c7f360f ("Gitlab: Rework sjg-lab calling test.py to be closer to test.py stage") the leading "and " part of the usage under qemu-x86_64 wasn't removed when it should have been. Do so now. Fixes: c7f360f ("Gitlab: Rework sjg-lab calling test.py to be closer to test.py stage") Reviewed-by: Simon Glass <simon.glass@canonical.com> Signed-off-by: Tom Rini <trini@konsulko.com>
This patch supports loading .dtb files from the /boot/extlinux/dtbs dirictory in an OreSat linux image built using image_builder at https://github.com/oresat/oresat-linux. This does NOT include support for loading FIT images in the SPL. Modify files: - board/ti/am335x/board.c - add logic to select oresat custom boards - board/ti/am335x/board.h - add board_is_* functions - board/ti/am335x/mux.c - add logic to select mux for oresat boards - include/configs/am335x_evm.h - add logic to load the correct .dtb for the selected oresat board Pass test using eeprom board string set to OSC3TEST that loads am335x_boneblack.dtb. This allows easy testing on a beaglebone black. OreSat boards are very similar to the Pocket Beagle (pb) or Beaglebone Black (bone_lt) so much of the boot configuration is based from those boards.
Remove OSC3TEST and set boot delay to zero. This was used for testing on a beaglebone black. A boot delay of zero skips past the timed prompt for entering the u-boot console. Note: you can still enter the u-boot console by holding down the spacebar during boot. Add oresat specific modifications to the initial pinmux configuration.
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This brings our fork up to date with the latest stable branch of mainline u-boot.