Phases:
- A single-cycle implementation of MIPS processor
- Cache memory added to a single-cycle implementation of the MIPS processor
- Pipelined implementation of MIPS processor
- Branch Prediction using Saturation Counter in Pipelined implementation of MIPS processor
Bonus point: Resolving data hazards using "forwarding" method
| Team Member | Student ID |
|---|---|
| AmirHossein Razlighi | 99102423 |
| Mohammad Parsa Bashari | 400104812 |
| Mohsen Ghasemi | 400105166 |