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3 changes: 3 additions & 0 deletions .gitmodules
Original file line number Diff line number Diff line change
@@ -1,3 +1,6 @@
[submodule "ihp13/pdk"]
path = ihp13/pdk
url = https://github.com/IHP-GmbH/IHP-Open-PDK
[submodule "circumspect"]
path = circumspect
url = https://github.com/schilkp/circumspect.git
9 changes: 9 additions & 0 deletions Bender.yml
Original file line number Diff line number Diff line change
Expand Up @@ -61,6 +61,15 @@ sources:
files:
- yosys/out/croc_chip_yosys_debug.v

- target: cspect
defines:
CSPECT: ~
include_dirs:
- circumspect/include
files:
- circumspect/include/cspect_pkg.sv
- rtl/test/croc_cspect.sv

- target: any(simulation, verilator)
files:
- rtl/test/tb_croc_pkg.sv
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13 changes: 10 additions & 3 deletions Makefile
Original file line number Diff line number Diff line change
Expand Up @@ -13,6 +13,7 @@ YOSYS ?= yosys
OPENROAD ?= openroad
KLAYOUT ?= klayout
VSIM ?= vsim
CARGO ?= cargo

# Directories
# directory of the path to the last called Makefile (this one)
Expand Down Expand Up @@ -62,6 +63,12 @@ sw: $(SW_HEX)
##################
# RTL Simulation #
##################
# CircumSpect DPI library
CSPECT_LIB := $(PROJ_DIR)/circumspect/target/release/libcspect.a

$(CSPECT_LIB): circumspect/Cargo.toml
cd circumspect; $(CARGO) build --release --lib

# Questasim/Modelsim/vsim
VLOG_ARGS = -svinputport=compat
VSIM_ARGS = -t 1ns -voptargs=+acc
Expand Down Expand Up @@ -98,10 +105,10 @@ VERILATOR_ARGS += --x-assign fast --x-initial fast
VERILATOR_CFLAGS += -O3 -march=native -mtune=native

verilator/croc.f: Bender.lock Bender.yml
$(BENDER) script verilator -t rtl -t verilator -t cve2_include_tracer -DSYNTHESIS -DVERILATOR -DTRACE_EXECUTION > $@
$(BENDER) script verilator -t rtl -t verilator -t cve2_include_tracer -t cspect -DSYNTHESIS -DVERILATOR -DTRACE_EXECUTION > $@

verilator/obj_dir/Vtb_croc_soc: verilator/croc.f $(SW_HEX)
cd verilator; $(VERILATOR) $(VERILATOR_ARGS) -O3 --top tb_croc_soc -f croc.f
verilator/obj_dir/Vtb_croc_soc: verilator/croc.f $(CSPECT_LIB) $(SW_HEX)
cd verilator; $(VERILATOR) $(VERILATOR_ARGS) -O3 --top tb_croc_soc -f croc.f $(CSPECT_LIB)

## Simulate RTL using Verilator
verilator: verilator/obj_dir/Vtb_croc_soc
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1 change: 1 addition & 0 deletions circumspect
Submodule circumspect added at b4ca54
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