Phy changes for kaanapali-pcie #389
Closed
Conversation
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
The commit a43ac32 ("PCI: Set up bridge resources earlier") moved bridge window resources set up earlier than before. The change was necessary to support another change that got pulled on the last minute due to breaking s390 and other systems. The presence of valid bridge window resources earlier than before allows pci_assign_unassigned_root_bus_resources() call from pci_host_probe() assign the bridge windows. Some host bridges, however, have to wait first for the link up event before they can enumerate successfully (see e.g. qcom_pcie_global_irq_thread()) and thus the bus has not been enumerated yet while calling pci_host_probe(). Calling pci_assign_unassigned_root_bus_resources() without results from enumeration can result in sizing bridge windows with too small sizes which cannot be later corrected after the enumeration has completed because bridge windows have become pinned in place by the other resources. Interestingly, it seems pci_read_bridge_bases() is not called at all in the problematic case and the bridge window resource type setup is done by pci_bridge_check_ranges() and sizing by the usual resource fitting logic. The root problem behind all this looks pretty generic. If resource fitting is called too early, the hotplug reservation and old size lower bounding cause the bridge windows to be assigned without children but with non-zero size, which leads to these pinning problems. As such, this can likely be solved on the general level but the solution does not look trivial. As the commit a43ac32 ("PCI: Set up bridge resources earlier") was prequisite for other change that did not end up into kernel yet, revert it to resolve the resource assignment failures and give time to code and test a generic solution. Reported-by: Val Packett <val@packett.cool> Reported-by: Guenter Roeck <linux@roeck-us.net> Fixes: a43ac32 ("PCI: Set up bridge resources earlier") Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> Link: https://patch.msgid.link/20251014163602.17138-1-ilpo.jarvinen@linux.intel.com
…hy bindings for qcs8300 The gcc_aux_clk is not required by the PCIe PHY on qcs8300 and is not specified in the device tree node. Hence, move the qcs8300 phy compatibility entry into the list of PHYs that require six clocks. Removed the phy_aux clock from the PCIe PHY binding as it is no longer used by any instance. Link: https://lore.kernel.org/all/20251024095609.48096-2-ziyue.zhang@oss.qualcomm.com/ Fixes: e46e59b ("dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Document the QCS8300 QMP PCIe PHY Gen4 x2") Signed-off-by: Ziyue Zhang <ziyue.zhang@oss.qualcomm.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
…Glymur QMP PCIe PHY The fifth PCIe instance on Glymur has a Gen5 4-lane PHY. Document it as a separate compatible. Link: https://lore.kernel.org/all/20251103-glymur-pcie-upstream-v6-1-18a5e0a538dc@oss.qualcomm.com/ Signed-off-by: Prudhvi Yarlagadda <quic_pyarlaga@quicinc.com> Signed-off-by: Wenbin Yao <wenbin.yao@oss.qualcomm.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
The new Glymur SoC bumps up the HW version of QMP phy to v8.50 for PCIE g5x4. Add the new PCS offsets in a dedicated header file. Link: https://lore.kernel.org/all/20251103-glymur-pcie-upstream-v6-2-18a5e0a538dc@oss.qualcomm.com/ Signed-off-by: Prudhvi Yarlagadda <quic_pyarlaga@quicinc.com> Signed-off-by: Wenbin Yao <wenbin.yao@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
Add support for Gen5 x4 PCIe QMP PHY found on Glymur platform. Link: https://lore.kernel.org/all/20251103-glymur-pcie-upstream-v6-3-18a5e0a538dc@oss.qualcomm.com/ Signed-off-by: Prudhvi Yarlagadda <quic_pyarlaga@quicinc.com> Signed-off-by: Wenbin Yao <wenbin.yao@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Acked-by: Manivannan Sadhasivam <mani@kernel.org> Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
…en4 2-lanes PHY The fourth and sixth PCIe instances on Glymur are both Gen4 2-lane PHY. So document the compatible. Link: https://lore.kernel.org/all/20251015-phy-qcom-pcie-add-glymur-v1-1-1af8fd14f033@linaro.org/ Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Glymur platform has two Gen4 2-lanes controllers, the fourth and sixth instances. Add support for their PHYs. Link: https://lore.kernel.org/all/20251015-phy-qcom-pcie-add-glymur-v1-2-1af8fd14f033@linaro.org/ Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
… compatible Document compatible for the QMP PCIe PHY on Kaanapali platform. Link:https://lore.kernel.org/all/20251124-kaanapali-pcie-phy-v4-1-d04ee9cca83b@oss.qualcomm.com/ Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
…egister offsets Kaanapali SoC uses QMP PHY with version v8 for PCIe Gen3 x2, but requires a completely unique qserdes-txrx register offsets compared to existing v8 offsets. Hence, add a dedicated header file containing the FULL SET of qserdes-txrx register definitions required for Kaanapali's PCIe PHY operation. Link: https://lore.kernel.org/all/20251124-kaanapali-pcie-phy-v4-2-d04ee9cca83b@oss.qualcomm.com/ Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
Kaanapali SoC uses QMP phy with version v8 for PCIe Gen3 x2. Add the new PCS PCIE specific offsets in a dedicated header file. Link: https://lore.kernel.org/all/20251124-kaanapali-pcie-phy-v4-3-d04ee9cca83b@oss.qualcomm.com/ Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
Some qserdes-com register offsets for the v8 PHY were previously omitted, as they were not needed by earlier v8 PHY initialization sequences. Add these missing v8 register offsets now required to support PCIe QMP PHY on Kaanapali platform. Link: https://lore.kernel.org/all/20251124-kaanapali-pcie-phy-v4-4-d04ee9cca83b@oss.qualcomm.com/ Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
Add QMP PCIe PHY support for the Kaanapali platform. Link: https://lore.kernel.org/all/20251124-kaanapali-pcie-phy-v4-5-d04ee9cca83b@oss.qualcomm.com/ Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
krishnachaitanya-linux
force-pushed
the
tech/bus/pci/all
branch
from
205830c to
94a1b72
Compare
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
5 participants
Add this suggestion to a batch that can be applied as a single commit.
This suggestion is invalid because no changes were made to the code.
Suggestions cannot be applied while the pull request is closed.
Suggestions cannot be applied while viewing a subset of changes.
Only one suggestion per line can be applied in a batch.
Add this suggestion to a batch that can be applied as a single commit.
Applying suggestions on deleted lines is not supported.
You must change the existing code in this line in order to create a valid suggestion.
Outdated suggestions cannot be applied.
This suggestion has been applied or marked resolved.
Suggestions cannot be applied from pending reviews.
Suggestions cannot be applied on multi-line comments.
Suggestions cannot be applied while the pull request is queued to merge.
Suggestion cannot be applied right now. Please check back later.
No description provided.