Wip/matt auld/rc6 wa bb playground gen9

drivers/gpu/drm/i915/Makefile

@@ -93,6 +93,13 @@ i915-y += dvo_ch7017.o \
 # virtual gpu code
 i915-y += i915_vgpu.o
 
+# perf code
+i915-y += i915_perf.o \
+	  i915_oa_hsw.o \
+	  i915_oa_bdw.o \
+	  i915_oa_chv.o \
+	  i915_oa_skl.o
+
 # legacy horrors
 i915-y += i915_dma.o
 

drivers/gpu/drm/i915/i915_cmd_parser.c

@@ -439,7 +439,7 @@ static const struct drm_i915_reg_descriptor gen7_render_regs[] = {
 	REG64(CL_PRIMITIVES_COUNT),
 	REG64(PS_INVOCATION_COUNT),
 	REG64(PS_DEPTH_COUNT),
-	REG32(OACONTROL), /* Only allowed for LRI and SRM. See below. */
+	REG32(GEN7_OACONTROL), /* Only allowed for LRI and SRM. See below. */
 	REG64(MI_PREDICATE_SRC0),
 	REG64(MI_PREDICATE_SRC1),
 	REG32(GEN7_3DPRIM_END_OFFSET),
@@ -1023,7 +1023,7 @@ static bool check_cmd(const struct intel_engine_cs *ring,
 			 * to the register. Hence, limit OACONTROL writes to
 			 * only MI_LOAD_REGISTER_IMM commands.
 			 */
-			if (reg_addr == OACONTROL) {
+			if (reg_addr == GEN7_OACONTROL) {
 				if (desc->cmd.value == MI_LOAD_REGISTER_MEM) {
 					DRM_DEBUG_DRIVER("CMD: Rejected LRM to OACONTROL\n");
 					return false;

drivers/gpu/drm/i915/i915_debugfs.c

@@ -1970,6 +1970,7 @@ static int i915_context_status(struct seq_file *m, void *unused)
 
 static void i915_dump_lrc_obj(struct seq_file *m,
 			      struct intel_engine_cs *ring,
+			      struct intel_context *ctx,
 			      struct drm_i915_gem_object *ctx_obj)
 {
 	struct page *page;
@@ -1984,7 +1985,7 @@ static void i915_dump_lrc_obj(struct seq_file *m,
 	}
 
 	seq_printf(m, "CONTEXT: %s %u\n", ring->name,
-		   intel_execlists_ctx_id(ctx_obj));
+		   intel_execlists_ctx_id(ctx));
 
 	if (!i915_gem_obj_ggtt_bound(ctx_obj))
 		seq_puts(m, "\tNot bound in GGTT\n");
@@ -2033,7 +2034,7 @@ static int i915_dump_lrc(struct seq_file *m, void *unused)
 	list_for_each_entry(ctx, &dev_priv->context_list, link) {
 		for_each_ring(ring, dev_priv, i) {
 			if (ring->default_context != ctx)
-				i915_dump_lrc_obj(m, ring,
+				i915_dump_lrc_obj(m, ring, ctx,
 						  ctx->engine[i].state);
 		}
 	}
@@ -2112,7 +2113,7 @@ static int i915_execlists(struct seq_file *m, void *data)
 
 			ctx_obj = head_req->ctx->engine[ring_id].state;
 			seq_printf(m, "\tHead request id: %u\n",
-				   intel_execlists_ctx_id(ctx_obj));
+				   intel_execlists_ctx_id(head_req->ctx));
 			seq_printf(m, "\tHead request tail: %u\n",
 				   head_req->tail);
 		}

drivers/gpu/drm/i915/i915_dma.c

@@ -170,6 +170,16 @@ static int i915_getparam(struct drm_device *dev, void *data,
 	case I915_PARAM_HAS_RESOURCE_STREAMER:
 		value = HAS_RESOURCE_STREAMER(dev);
 		break;
+	case I915_PARAM_SLICE_MASK:
+		value = INTEL_INFO(dev_priv)->slice_mask;
+		if (!value)
+			return -ENODEV;
+		break;
+	case I915_PARAM_SUBSLICE_MASK:
+		value = INTEL_INFO(dev_priv)->subslice_mask;
+		if (!value)
+			return -ENODEV;
+		break;
 	default:
 		DRM_DEBUG("Unknown parameter %d\n", param->param);
 		return -EINVAL;
@@ -554,16 +564,20 @@ static void cherryview_sseu_info_init(struct drm_device *dev)
 	info = (struct intel_device_info *)&dev_priv->info;
 	fuse = I915_READ(CHV_FUSE_GT);
 
+	info->slice_mask = 1;
 	info->slice_total = 1;
+	info->subslice_mask = 0;
 
 	if (!(fuse & CHV_FGT_DISABLE_SS0)) {
+		info->subslice_mask |= 0x1;
 		info->subslice_per_slice++;
 		eu_dis = fuse & (CHV_FGT_EU_DIS_SS0_R0_MASK |
 				 CHV_FGT_EU_DIS_SS0_R1_MASK);
 		info->eu_total += 8 - hweight32(eu_dis);
 	}
 
 	if (!(fuse & CHV_FGT_DISABLE_SS1)) {
+		info->subslice_mask |= 0x2;
 		info->subslice_per_slice++;
 		eu_dis = fuse & (CHV_FGT_EU_DIS_SS1_R0_MASK |
 				 CHV_FGT_EU_DIS_SS1_R1_MASK);
@@ -592,9 +606,9 @@ static void gen9_sseu_info_init(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_device_info *info;
-	int s_max = 3, ss_max = 4, eu_max = 8;
+	int s_max = 3, ss_max = 3, eu_max = 8;
 	int s, ss;
-	u32 fuse2, s_enable, ss_disable, eu_disable;
+	u32 fuse2, s_enable, ss_disable, eu_disable, ss_mask;
 	u8 eu_mask = 0xff;
 
 	info = (struct intel_device_info *)&dev_priv->info;
@@ -604,11 +618,20 @@ static void gen9_sseu_info_init(struct drm_device *dev)
 	ss_disable = (fuse2 & GEN9_F2_SS_DIS_MASK) >>
 		     GEN9_F2_SS_DIS_SHIFT;
 
+	info->slice_mask = s_enable;
 	info->slice_total = hweight32(s_enable);
+
 	/*
 	 * The subslice disable field is global, i.e. it applies
-	 * to each of the enabled slices.
-	*/
+	 * to each of the enabled slices. We generalise this into
+	 * a mask covering all slices...
+	 */
+	ss_mask = ss_disable ^ ((1 << ss_max) - 1);
+	for (s = 0; s < s_max; s++) {
+	    if (s_enable & (0x1 << s))
+		info->subslice_mask |= ss_mask << (ss_max * s);
+	}
+
 	info->subslice_per_slice = ss_max - hweight32(ss_disable);
 	info->subslice_total = info->slice_total *
 			       info->subslice_per_slice;
@@ -675,6 +698,7 @@ static void broadwell_sseu_info_init(struct drm_device *dev)
 	const int s_max = 3, ss_max = 3, eu_max = 8;
 	int s, ss;
 	u32 fuse2, eu_disable[s_max], s_enable, ss_disable;
+	u32 ss_mask;
 
 	fuse2 = I915_READ(GEN8_FUSE2);
 	s_enable = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT;
@@ -690,12 +714,20 @@ static void broadwell_sseu_info_init(struct drm_device *dev)
 
 
 	info = (struct intel_device_info *)&dev_priv->info;
+	info->slice_mask = s_enable;
 	info->slice_total = hweight32(s_enable);
 
 	/*
 	 * The subslice disable field is global, i.e. it applies
-	 * to each of the enabled slices.
+	 * to each of the enabled slices. We generalize this into
+	 * a mask covering all slices...
 	 */
+	ss_mask = ss_disable ^ ((1 << ss_max) - 1);
+	for (s = 0; s < s_max; s++) {
+		if (s_enable & (0x1 << s))
+			info->subslice_mask |= ss_mask << (ss_max * s);
+	}
+
 	info->subslice_per_slice = ss_max - hweight32(ss_disable);
 	info->subslice_total = info->slice_total * info->subslice_per_slice;
 
@@ -893,6 +925,11 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
 	mutex_init(&dev_priv->csr_lock);
 	mutex_init(&dev_priv->av_mutex);
 
+	/* Must at least be initialized before trying to pin any context
+	 * which i915_perf hooks into.
+	 */
+	i915_perf_init(dev);
+
 	intel_pm_setup(dev);
 
 	intel_display_crc_init(dev);
@@ -1139,6 +1176,7 @@ int i915_driver_unload(struct drm_device *dev)
 		return ret;
 	}
 
+	i915_perf_fini(dev);
 	intel_power_domains_fini(dev_priv);
 
 	intel_gpu_ips_teardown();
@@ -1329,6 +1367,7 @@ const struct drm_ioctl_desc i915_ioctls[] = {
 	DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW),
 	DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW),
 	DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW),
+	DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, DRM_RENDER_ALLOW),
 };
 
 int i915_max_ioctl = ARRAY_SIZE(i915_ioctls);