Overview

FPGA accelerator implementation from paper An FPGA Accelerator for Genome Variant Calling published at ACM TRETS.

The paper presents a set of FPGA accelerators of LoFreq that run up to 50X faster than the multiprocess CPU baseline. Fine-grained pipelining and prefetching are implemented (in HLS C/C++) and tuned to achieve the speedup.

This work is a fun mixture of software (writing/tuning low-level kernel for the HLS compiler) and hardware (physical implementation, timing closure) work. Incredibly fun project.

More details here in the slide deck.

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Source Directory

├── Makefile: commands to build .xo and .xclbin.
├── README.md
└── src 
    ├── Makefile: commands to run Vitis HLS sythesis.
    ├── hls.tcl: tcl script to set up and run HLS C sythesis.
    ├── krnl.c: HLS C source code.
    ├── krnl.h: header file.
    ├── runPre.tcl: building configuration.
    └── u250-krnl.cfg: Vivado implementation strategy control and SLR connectivity specification.

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How to Build

1. Make sure Xilinx Vitis is installed.
2. Change configurations in Makefile or src/u250-krnl.cfg if necessary.
3. Run make xclbin. For Vitis 2021 or prior versions, consider running make xclbin using faketime with a timestamp earlier than 20220101.

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Reference

@article{xu2023fpga,
  title={An FPGA Accelerator for Genome Variant Calling},
  author={Xu, Tiancheng and Rixner, Scott and Cox, Alan L},
  journal={ACM Transactions on Reconfigurable Technology and Systems},
  volume={16},
  number={4},
  pages={1--29},
  year={2023},
  publisher={ACM New York, NY}
}