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Add gsw1xx htdocs #50

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0225e12
LINK_TYPE_DSA_GSW1XX: add EDSA protocol for GSW1xx family.
peteraxis Nov 24, 2025
5a5a3da
Merge branch 'the-tcpdump-group:master' into master
peteraxis Nov 25, 2025
b6461be
Merge branch 'the-tcpdump-group:master' into gsw1xx
peteraxis Nov 28, 2025
72627da
Merge branch 'the-tcpdump-group:master' into gsw1xx
peteraxis Dec 5, 2025
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11 changes: 11 additions & 0 deletions htmlsrc/linktypes.html
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Expand Up @@ -1937,6 +1937,17 @@ <h2 class="title">
</td>
</tr>

<tr>
<td class="symbol">LINKTYPE_DSA_TAG_GSW1XX</td>
<td class="number">302</td>
<td class="symbol">DLT_DSA_TAG_GSW1XX</td>
<td>
<a href="linktypes/LINKTYPE_DSA_TAG_GSW1XX.html">Ethernet
frames, with a MaxLinear/Intel/Infinion switch tag inserted</a>.
</td>
</tr>


<tr>
<td class="symbol">LINKTYPE_IEEE802_15_4_TAP</td>
<td class="number">283</td>
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30 changes: 30 additions & 0 deletions htmlsrc/linktypes/LINKTYPE_DSA_TAG_GSW1XX.html
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<!-- Start of LINKTYPE_DSA_TAG_GSW1XX section -->
<div class="post">
<h2 class="title">
LINKTYPE_DSA_TAG_GSW1XX
</h2>
<div class="entry">
<h3 class="subtitle">Packet structure</h3>
<pre>
+--------------------------------+
| Destination Address (6 octets) |
+--------------------------------+
| Source Address (6 octets) |
+--------------------------------+
| GSW1XX switch tag (8 octets) |
+--------------------------------+
| EtherType/Length (2 octets) |
+--------------------------------+
| Payload |
. .
. .
. .
</pre>
<h3 class="subtitle">Description</h3>
<p>
A <a href="../linktypes/gsw1xx-switch-tag.html">GSW1XX switch tag</a>
is inserted in the Ethernet header before the EtherType/Length field.
</p>
</div>
</div>
<!-- End of LINKTYPE_DSA_TAG_GSW1XX section -->
91 changes: 91 additions & 0 deletions htmlsrc/linktypes/gsw1xx-switch-tag.html
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<!-- Start of gsw1xx switch tag section -->
<div class="post">
<h2 class="title">gsw1xx</h2>
<div class="entry">
The protocol
is used by GSW120, GSW140, GSW141, GSW145 chips and has a history with products from Infineon, Intel and MaxLinear.
The protocol information is based on the MaxLinear Data Sheet Revision 1.4.
<h4 class="subtitle">Switch tag structure</h4>
<ul>
The gsw1xx EDSA tagged frames contain a proprietary tag inserted between the source address field and the
EtherType/length field in the Ethernet header.
The EDSA tag is 8 octets. It contains a programmable EtherType value
and a standard DSA tag.
Ingress and Egress have different formats. If byte 6&7 is not
zero it is a egress packet.
</ul>
Format of (Ethertyped) Ingress tagged frames:
<pre>
+0 +----+----+----+----+----+----+----+----+ +-
| Prog. DSA Ether Type [15:8] | | (8-byte) EDSA Tag
+1 +----+----+----+----+----+----+----+----+ | Contains a programmable Ether type.
| Prog. DSA Ether Type [7:0] | | +
+1 +----+----+----+----+----+----+----+----+ | | (6-byte) Special Tag Content
|PME[7] TCE[6] TSE[5] FNL[4] TTC[3:0] | | |
+1 +----+----+----+----+----+----+----+----+ | |
| TEPML [7:0] | | |
+1 +----+----+----+----+----+----+----+----+ | |
| TEPMH [7:0] | | |
+1 +----+----+----+----+----+----+----+----+ | |
| Res[7:5] IE[4] SP[3:0] | | |
+1 +----+----+----+----+----+----+----+----+ | |
| Res [7:0] all zero | | |
+1 +----+----+----+----+----+----+----+----+ | |
| Res [7:0] all zero | | |
+1 +----+----+----+----+----+----+----+----+ +- +-
</pre>
Format of (Ethertyped) Egress tagged frames:
<pre>

+0 +----+----+----+----+----+----+----+----+ +-
| Prog. DSA Ether Type [15:8] | | (8-byte) EDSA Tag
+1 +----+----+----+----+----+----+----+----+ | Contains a programmable Ether type.
| Prog. DSA Ether Type [7:0] | | +
+1 +----+----+----+----+----+----+----+----+ | | (6-byte) Special Tag Content
| TC[7:4] IPN [3:0] | | |
+1 +----+----+----+----+----+----+----+----+ | |
| PPPOE[7] IPV[6] IPO[5:0] | | |
+1 +----+----+----+----+----+----+----+----+ | |
| DLPML [7:0] | | |
+1 +----+----+----+----+----+----+----+----+ | |
| DLPMR [7:0] | | |
+1 +----+----+----+----+----+----+----+----+ | |
| MI[7] KL2UM[6] PLHB[5:0] | | |
+1 +----+----+----+----+----+----+----+----+ | |
| PLLB [7:0] | | |
+1 +----+----+----+----+----+----+----+----+ +- +-

</pre>
<div>
<h4 class="subtitle">Bit field abbreviations</h4>
<ul>
<li>PME: Port map enable </li>
<li>IPN: Ingress port number</li>
<li>TCE: Traffic class enable</li>
<li>TSE: Time stamp enable</li>
<li>FNL: Force no learning</li>
<li>TC: Traffic class</li>
<li>IPV: IPv4 packet</li>
<li>IPO: IP offset</li>
<li>SP: Source port</li>
<li>IE: Interrupt enable</li>
<li>PPPOE: ppp-over-ethernet</li>
<li>DLPML: Destination logical port map low bits.</li>
<li>DLPMR: Destination logical port map high (reserved)</li>
<li>MI: Mirror indication</li>
<li>KL2UM Known l2 unicast/multicast mac.</li>
<li>PLHB: Packet Length High Bits</li>
<li>PLLB: Packet Length Low Bits</li>
<li>TEPML: Target egress port maps low bits</li>
<li>TEPMH: Target egress port maps high bits (reserved)</li>
<li>Res: Reserved</li>
</ul>
</div>
<h5 class="notes">Notes</h5>
Port mapping is a switch internal function for multi-cast and vlan
routing and need custom firmware rules to be active.
<br><br>
Precise Time Stamping indication according to IEEE 1588v2.
</div>
</div>
<!-- End of gsw1xx switch tag section -->
11 changes: 11 additions & 0 deletions linktypes.html
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</td>
</tr>

<tr>
<td class="symbol">LINKTYPE_DSA_TAG_GSW1XX</td>
<td class="number">302</td>
<td class="symbol">DLT_DSA_TAG_GSW1XX</td>
<td>
<a href="linktypes/LINKTYPE_DSA_TAG_GSW1XX.html">Ethernet
frames, with a MaxLinear/Intel/Infinion switch tag inserted</a>.
</td>
</tr>


<tr>
<td class="symbol">LINKTYPE_IEEE802_15_4_TAP</td>
<td class="number">283</td>
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90 changes: 90 additions & 0 deletions linktypes/LINKTYPE_DSA_TAG_GSW1XX.html
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<!DOCTYPE html>
<html lang="en">

<!-- HEAD -->
<head>
<meta charset="utf-8">
<title>LINKTYPE_DSA_TAG_GSW1XX | TCPDUMP &amp; LIBPCAP</title>
<meta name="description" content="Web site of Tcpdump and Libpcap">
<link href="../style.css" rel="stylesheet" type="text/css" media="screen">
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<!-- Start of LINKTYPE_DSA_TAG_GSW1XX section -->
<div class="post">
<h2 class="title">
LINKTYPE_DSA_TAG_GSW1XX
</h2>
<div class="entry">
<h3 class="subtitle">Packet structure</h3>
<pre>
+--------------------------------+
| Destination Address (6 octets) |
+--------------------------------+
| Source Address (6 octets) |
+--------------------------------+
| GSW1XX switch tag (8 octets) |
+--------------------------------+
| EtherType/Length (2 octets) |
+--------------------------------+
| Payload |
. .
. .
. .
</pre>
<h3 class="subtitle">Description</h3>
<p>
A <a href="../linktypes/gsw1xx-switch-tag.html">GSW1XX switch tag</a>
is inserted in the Ethernet header before the EtherType/Length field.
</p>
</div>
</div>
<!-- End of LINKTYPE_DSA_TAG_GSW1XX section -->
</div>
<!-- END OF PAGE CONTENTS -->

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