feat(RV64): implement and register interrupt controller#676
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PeterWrighten wants to merge 2 commits intomainfrom
Open
feat(RV64): implement and register interrupt controller#676PeterWrighten wants to merge 2 commits intomainfrom
PeterWrighten wants to merge 2 commits intomainfrom
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Signed-off-by: Enigamict <atsuki.takata@tier4.jp>
- Add RiscvPlic implementing InterruptController trait via RISC-V PLIC - Add ACLINT-based IPI (send_ipi, send_ipi_broadcast) via MSIP registers - Add M-mode trap handler in boot.S for IPI and timer interrupt routing - Add handle_irqs() for RISC-V to dispatch IRQs from M-mode trap handler - Add init_non_primary() per-hart PLIC threshold and software interrupt setup - Register PLIC during primary hart boot sequence - Expose NUM_CPUS for per-CPU IPI targeting
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In order to close #487
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