Design, verification and ASIC implementation of a complete RISC-V CPU with: five stages pipeline, forwarding, automatic hazard detection, Branch Target Buffer using LRU replacement policy, absolute value custom instruction.

C++ implementation of computer architecture branch prediction algorithms with comprehensive Python analysis tools. Features static and two-bit dynamic branch predictors, configurable Branch Target Buffer (BTB) with LRU replacement, automated performance testing and visualization of prediction accuracy and processor overhead metrics.