IHP 130nm ASIC tapeout of a 2x2 bfloat16 matrix matrix multiplication with DFT infrastructure. Iteration on the previous accelerator taped out on GF180.
-
Updated
Mar 25, 2026 - Verilog
#
sg13g2
Here are 3 public repositories matching this topic...
Experimental 4x8 configuration for Tiny Tapeout IHP
-
Updated
Dec 8, 2025 - Verilog
Improve this page
Add a description, image, and links to the sg13g2 topic page so that developers can more easily learn about it.
Add this topic to your repo
To associate your repository with the sg13g2 topic, visit your repo's landing page and select "manage topics."