Learn Digital Verilog: RTL Design with Verilog and SystemVerilog

A comprehensive, modular learning path for mastering RTL (Register Transfer Level) design using Verilog and SystemVerilog with progressive complexity levels. This project provides a complete educational resource with examples, testbenches, and documentation covering all aspects of digital circuit design from fundamentals to advanced techniques.

📋 Table of Contents

• Overview
• Features
• Prerequisites
• Quick Start
• Project Structure
• Documentation
• Modules
• Installation
• Usage
• Contributing
• License
• Acknowledgments

🎯 Overview

This project is a complete educational resource for learning RTL design using Verilog and SystemVerilog. It provides:

• 10 Progressive Modules: From installation and digital logic fundamentals to advanced design techniques
• Comprehensive Examples: Working code examples with detailed explanations
• Complete Testbenches: Both iverilog and Verilator testbenches for each module
• Automated Scripts: Installation and orchestration scripts for easy setup
• Full Documentation: Detailed guides covering all concepts and usage
• CORE Repository Integration: References to professional RTL designs for comparison and learning
• Dual Simulator Support: Examples work with both iverilog and Verilator

Why RTL Design?

• Industry Standard: RTL design is the foundation of digital circuit design
• IEEE Standards: Based on IEEE 1364-2005 (Verilog) and IEEE 1800-2017 (SystemVerilog)
• Career Relevance: Essential skill for digital design engineers
• Open Source Tools: Works with free, open-source simulators (iverilog, Verilator)
• Practical Application: Directly applicable to FPGA and ASIC design

Learning Approach

This course bridges theory and practice:

• Theory: Digital logic fundamentals, Boolean algebra, circuit concepts
• Practice: Hands-on Verilog/SystemVerilog coding with real examples
• Reference: Comparison with professional designs from the CORE repository
• Progressive: Builds from simple gates to complex system integration

✨ Features

• ✅ Complete RTL Coverage: From digital logic fundamentals to system integration
• ✅ Progressive Learning: 10 modules from beginner to advanced
• ✅ Practical Examples: Real-world RTL design scenarios
• ✅ Automated Setup: One-command installation scripts
• ✅ Dual Simulator Support: Examples for both iverilog and Verilator
• ✅ CORE Repository Integration: References to professional designs
• ✅ Comprehensive Documentation: Detailed guides for every concept
• ✅ Production Quality: Best practices and industry patterns
• ✅ Exercises: Hands-on practice for each module
• ✅ Waveform Analysis: GTKWave integration for debugging

📚 Prerequisites

Required Knowledge

• Basic Computer Science: Understanding of programming concepts
• No Prior Digital Logic Required: Course starts from fundamentals
• Basic Math: Understanding of binary numbers (covered in Module 1)

System Requirements

• Operating System: Linux, macOS, or Windows (WSL2 recommended)
• Simulators: Icarus Verilog (iverilog) and/or Verilator
• Waveform Viewer: GTKWave (optional but recommended)
• Memory: Minimum 4GB RAM (8GB+ recommended)
• Disk Space: ~2GB for tools and dependencies
• Build Tools: C++ compiler (GCC, Clang) for Verilator, Make

🚀 Quick Start

1. Clone the Repository

git clone <repository-url>
cd learn_digital_verilog

2. Install All Tools (Automated)

# Make scripts executable (Linux/Mac/WSL)
chmod +x scripts/*.sh

# Install all tools with default settings
./scripts/module0.sh

3. Run Your First Example

# Run Module 0 examples
./scripts/module0.sh

# Or run specific examples
./scripts/module0.sh --iverilog-basics
./scripts/module0.sh --verilator-basics

4. Start Learning

Begin with Module 0: Installation and Setup and follow the modules sequentially. See SYLLABUS1.md for the complete course structure.

📁 Project Structure

learn_digital_verilog/
├── docs/                      # Comprehensive documentation
│   ├── SYLLABUS1.md          # Complete course syllabus
│   ├── MODULE0.md            # Installation and setup guide
│   ├── MODULE1.md            # Digital logic fundamentals
│   ├── MODULE2.md            # Verilog/SystemVerilog fundamentals
│   ├── MODULE3.md            # Combinational logic design
│   ├── MODULE4.md            # Sequential logic and registers
│   ├── MODULE5.md            # State machines and control logic
│   ├── MODULE6.md            # Arithmetic circuits and data paths
│   ├── MODULE7.md            # Memory and storage elements
│   ├── MODULE8.md            # Advanced design techniques
│   └── MODULE9.md            # Design integration and best practices
│
├── module0/                   # Installation and setup
│   ├── examples/             # Basic examples (iverilog, Verilator)
│   ├── dut/                   # Design Under Test (simple gates, counters)
│   └── tests/                 # Testbenches
├── module1/                   # Digital logic fundamentals
│   ├── examples/             # Number systems, Boolean algebra examples
│   ├── dut/                   # Basic gates, combinational circuits
│   └── tests/                 # Testbenches
├── module2/                   # Verilog/SystemVerilog fundamentals
├── module3/                   # Combinational logic design
├── module4/                   # Sequential logic and registers
├── module5/                   # State machines and control logic
├── module6/                   # Arithmetic circuits and data paths
├── module7/                   # Memory and storage elements
├── module8/                   # Advanced design techniques
├── module9/                   # Design integration and best practices
│
├── scripts/                   # Automation scripts
│   ├── module0.sh            # Install all tools
│   ├── module1.sh            # Run Module 1 examples
│   ├── ...                    # Module orchestrators
│   ├── install_*.sh          # Individual tool installers
│   └── uninstall_*.sh        # Tool uninstallers
│
└── README.md                  # This file

📖 Documentation

The docs/ directory contains comprehensive documentation for the entire learning path:

Core Documentation

• SYLLABUS1.md: Complete course syllabus with learning path, duration, and topics for all modules

Module Documentation

Each module has a dedicated guide with examples, exercises, and detailed explanations:

• MODULE0.md: Installation and Setup

  • System requirements, tool installation, environment setup
  • Automated installation scripts usage
  • First examples with iverilog and Verilator
  • CORE repository reference

• MODULE1.md: Digital Logic Fundamentals

  • Number systems (binary, hex, decimal)
  • Boolean algebra and logic gates
  • Truth tables and logic analysis
  • Combinational vs. sequential logic concepts
  • Mapping logic concepts to Verilog

• MODULE2.md: Verilog/SystemVerilog Fundamentals

  • Language basics and syntax
  • Data types and operators
  • Module structure and instantiation
  • Continuous assignments

• MODULE3.md: Combinational Logic Design

  • Design styles (continuous assignment, always_comb, case statements)
  • Common combinational circuits (MUX, decoder, encoder, comparator)
  • Arithmetic combinational circuits (adders, multipliers)
  • Parameterized designs and generate blocks

• MODULE4.md: Sequential Logic and Registers

  • Flip-flops and latches
  • Procedural blocks (always_ff, always_comb)
  • Register design and counters
  • Clock domain management
  • Reset strategies

• MODULE5.md: State Machines and Control Logic

  • FSM fundamentals (Mealy vs. Moore)
  • FSM implementation styles
  • Complex state machines
  • Control logic design

• MODULE6.md: Arithmetic Circuits and Data Paths

  • Adder architectures (ripple carry, carry lookahead)
  • Multipliers (array, Booth, Wallace tree)
  • ALU design
  • Data path implementation

• MODULE7.md: Memory and Storage Elements

  • ROM and RAM design
  • FIFO implementation
  • Cache memory basics
  • Memory controllers

• MODULE8.md: Advanced Design Techniques

  • SystemVerilog interfaces and modports
  • Packages and namespaces
  • Advanced generate constructs
  • Design patterns

• MODULE9.md: Design Integration and Best Practices

  • Design hierarchy and integration
  • Coding standards and style
  • Synthesis considerations
  • Performance optimization

🎓 Modules

Module 0: Installation and Setup

Set up your RTL design environment with all required tools:

• Icarus Verilog (iverilog) installation
• Verilator installation
• GTKWave for waveform viewing
• First "Hello World" examples
• CORE repository reference

Quick Start: ./scripts/module0.sh

Module 1: Digital Logic Fundamentals

Learn the essential foundation in digital logic:

• Number systems (binary, hex, decimal)
• Boolean algebra and logic gates
• Truth tables and logic analysis
• Combinational vs. sequential logic
• Mapping logic concepts to Verilog

Quick Start: ./scripts/module1.sh

Module 2: Verilog/SystemVerilog Fundamentals

Master the fundamental syntax and constructs:

• Language basics and module structure
• Data types and operators
• Continuous assignments
• Module instantiation

Quick Start: ./scripts/module2.sh

Module 3: Combinational Logic Design

Master combinational circuit design:

• Design styles (continuous assignment, always_comb, case)
• Common circuits (MUX, decoder, encoder, comparator)
• Arithmetic circuits (adders, multipliers)
• Parameterized designs

Quick Start: ./scripts/module3.sh

Module 4: Sequential Logic and Registers

Master sequential circuit design:

• Flip-flops and registers
• Procedural blocks
• Counters and shift registers
• Clock and reset strategies

Quick Start: ./scripts/module4.sh

Module 5: State Machines and Control Logic

Master finite state machine design:

• FSM fundamentals (Mealy vs. Moore)
• Implementation styles
• Complex state machines
• Control logic design

Quick Start: ./scripts/module5.sh

Module 6: Arithmetic Circuits and Data Paths

Master arithmetic circuit design:

• Adder architectures
• Multipliers
• ALU design
• Data path implementation

Quick Start: ./scripts/module6.sh

Module 7: Memory and Storage Elements

Master memory design:

• ROM and RAM design
• FIFO implementation
• Cache memory basics
• Memory controllers

Quick Start: ./scripts/module7.sh

Module 8: Advanced Design Techniques

Master advanced RTL design techniques:

• SystemVerilog interfaces and modports
• Packages and namespaces
• Advanced generate constructs
• Design patterns

Quick Start: ./scripts/module8.sh

Module 9: Design Integration and Best Practices

Master design integration and best practices:

• Design hierarchy and integration
• Coding standards and style
• Synthesis considerations
• Performance optimization
• Design reuse

Quick Start: ./scripts/module9.sh

🔧 Installation

Automated Installation (Recommended)

# Install all tools
./scripts/module0.sh

# Or install individual tools
./scripts/install_iverilog.sh
./scripts/install_verilator.sh
./scripts/install_gtkwave.sh

Individual Tool Installation

# Icarus Verilog
./scripts/install_iverilog.sh

# Verilator
./scripts/install_verilator.sh --source
# Or install specific version
./scripts/install_verilator.sh --version 5.044 --source
# Or install locally (no sudo required)
./scripts/install_verilator.sh --source --local

# GTKWave
./scripts/install_gtkwave.sh

Manual Installation

See MODULE0.md for detailed manual installation instructions.

💻 Usage

Running Examples

Each module has an orchestrator script to run examples and tests:

# Run all examples for a module
./scripts/module0.sh
./scripts/module1.sh
# ... etc

# Run specific examples
./scripts/module0.sh --iverilog-basics
./scripts/module0.sh --verilator-basics
./scripts/module1.sh --number-systems

Running Individual Examples

# iverilog example
cd module0/examples/iverilog_basics
make hello_world

# Verilator example
cd module0/examples/verilator_basics
make hello_world

# View waveforms
cd module0/examples/iverilog_basics
make gtkwave_example
gtkwave gtkwave_example.vcd

Using Both Simulators

This project supports both simulators:

• Icarus Verilog (iverilog): Great for learning, simple testbenches, waveform generation
• Verilator: Fast simulation, C++ testbenches, production-quality verification

Examples are provided for both, allowing you to choose based on your needs.

🤝 Contributing

Contributions are welcome! This project follows best practices for educational resources:

1. Code Quality: All code follows Verilog/SystemVerilog best practices with comprehensive comments
2. Documentation: Comprehensive docstrings and comments
3. Testing: Examples are tested and verified
4. Consistency: Follow existing patterns and structure

Contribution Guidelines

• Follow the existing code style and structure
• Add comprehensive comments to all code
• Update relevant documentation
• Test your changes thoroughly
• Follow the module structure for new examples
• Reference CORE repository for professional patterns

📄 License

This work is licensed under a Creative Commons Attribution 4.0 International License.

What this means:

• ✅ You are free to:

  • Share — copy and redistribute the material in any medium or format
  • Adapt — remix, transform, and build upon the material for any purpose, even commercially

• 📝 Under the following terms:

  • Attribution — You must give appropriate credit, provide a link to the license, and indicate if changes were made. You may do so in any reasonable manner, but not in any way that suggests the licensor endorses you or your use.

Attribution

When using this material, please include:

Based on "Learn Digital Verilog: RTL Design with Verilog and SystemVerilog" by Yongfu Li
Licensed under CC BY 4.0
https://creativecommons.org/licenses/by/4.0/

🙏 Acknowledgments

This project is built on the excellent work of:

• CORE Repository: Corpus Of RTL designs for EDA Research

  • Repository: https://github.com/universal-verification-methodology/core
  • 137 verified Verilog modules across 24 categories
  • Professional RTL design patterns and testbenches
  • Used as reference for best practices throughout this course

• Verilator: Fast Verilog/SystemVerilog simulator

  • Website: https://www.veripool.org/verilator/
  • GitHub: https://github.com/verilator/verilator
  • Open-source, high-performance simulation

• Icarus Verilog: Open-source Verilog simulator

  • Website: http://iverilog.wikia.com/
  • Simple, educational-friendly simulator

• GTKWave: Waveform viewer

  • Website: http://gtkwave.sourceforge.net/
  • Essential tool for debugging and analysis

• SystemVerilog: IEEE 1800-2017 Standard

  • Standard: IEEE 1800-2017
  • Language Reference Manual

• Verilog: IEEE 1364-2005 Standard

  • Standard: IEEE 1364-2005
  • Hardware Description Language

Educational Resources

• "Digital Design and Computer Architecture" by Harris & Harris
• "Verilog HDL" by Samir Palnitkar
• "SystemVerilog for Design" by Sutherland, Davidmann, and Flake
• IEEE Design & Test publications

📞 Support

For questions, issues, or contributions:

1. Check the documentation first
2. Review the SYLLABUS1.md for course structure
3. Check individual module documentation for specific topics
4. Reference CORE repository for professional examples
5. Open an issue for bugs or feature requests

📊 Project Statistics

• 10 Modules: Complete learning path from fundamentals to advanced
• 50+ Examples: Working code examples with detailed explanations
• 20+ Testbenches: Both iverilog and Verilator testbenches
• 15+ Scripts: Automation and orchestration
• 10+ Documentation Files: Comprehensive guides
• CORE Integration: References to 137 professional RTL designs

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Happy Learning! 🚀

Start your RTL design journey today with Module 0: Installation and Setup