Add support for string

[oscargus]

Based on the discussion in verilator/verilator#6879

Will have to test a bit more before removing from draft.

[oscargus]

Note that the file name here (and some more) was different than the actual, so the test passed as the "file not found" error was on stderr... I have renamed the files to correspond to the script.

[oscargus]

Not sure how much to test, but added tests for changed identifier (which can be handled) and changed value (which provides output). It uses the same printing for string errors as for vector errors, but that is maybe OK?

[oscargus]

It should also be noted that spaces in strings must be escaped, typically as \040 and that is not handled here (but shouldn't present a problem to detect changes, just non-ideal output). That was actually the reason I started to look into this as NVC and GHDL handles strings (and VHDL character) differently, so wanted input from SystemVerilog and therefore Verilator, to check which variants are available. Not sure if it is fst2vcd or the simulator that do the replacement, but would guess for fst2vcd since it should be possible to have spaces in fst.