Fix: Mask shift amount to 5 bits for SLL, SRL, and SRA instructions

[GabPGomes]

Bug Fix

First of all, congratulations on your work on this processor. You have used it to publish multiple articles in a relevant research area. My research focuses on verifying RISC-V processors, and I am using your design in my evaluation.
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The Issue

Currently, the shift logic in alu.vhd uses the entire 32-bit word of the rs2 operand (data2_i) to determine the shift amount. However, according to the RISC-V Unprivileged Architecture Specification (RV32I Base Integer Instruction Set), these instructions should only consider the lower 5 bits of the shift amount register.

From the RISC-V Specification (v20250508):

"SLL, SRL, and SRA perform logical left, logical right, and arithmetic right shifts on the value in register rs1 by the shift amount held in the lower 5 bits of register rs2."

How to Reproduce

Using the full word causes incorrect results if software leaves non-zero values in the upper bits of the shift amount register. The bug was exposed after applying the sra-01.elf test program from the riscv-arch-test repository. Specifically, this code snippet:

00000190 <inst_1>:
 190:	02000637          	lui	a2,0x2000
 194:	02000637          	lui	a2,0x2000
 198:	40c65833          	sra	a6,a2,a2
 19c:	010a2223          	sw	a6,4(s4)

The Fix

The shift amount is now explicitly masked to the 5 least significant bits (4 downto 0) before being converted to an integer. This ensures the hardware ignores the upper 27 bits of rs2 as required by the ISA.