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  • SeoulTech
  • 232, Gongneung-ro, Nowon-gu, Seoul, Republic of Korea

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youngyang00/README.md

Gwangsun Shin (youngyang00)

Current Position

  • SoC Design Engineer, Mobilint
    (2025–Present)

Interests

  • SoC RTL design and microarchitecture
  • RTL design for AI/vision accelerators
  • AXI4-based system design and integration
  • UVM-based verification
  • Hardware-efficient neural network optimization

Education

  • Seoul National University of Science and Technology
    B.S. in Electrical & Information Engineering (2019–2026)

Awards

  • Gold Prize, 2025 Korea Undergraduate Semiconductor Design Contest (ISE)
    Awarded for the project "FSRCNN-based Super Resolution Accelerator"

  • Silver Prize (2nd Place), 2024 IDEC Creative Circuit Design Challenge (Nov 8, 2024)
    Awarded for the project "Reusable PE Array CNN Accelerator"

Skills

  • HDL: Verilog, SystemVerilog
  • Verification: UVM
  • Tools: Xilinx Vivado/Vitis, Synopsys VCS
  • Languages: C/C++, Python

Contact

Pinned Loading

  1. FSRCNN-accelerater FSRCNN-accelerater Public

    This project implements a hardware-accelerated FSRCNN (Fast Super-Resolution Convolutional Neural Network) on FPGA, designed to upscale low-resolution images from 320×180 to 1280×720 (×4) and achie…

    VHDL 2 2

  2. axi4s-bicubic-upscaler axi4s-bicubic-upscaler Public

    This repository provides a hardware-optimized bicubic interpolation IP designed for real-time image scaling on FPGA platforms. The core is built on the AXI4-Stream protocol and supports full backpr…

    Verilog 1 1

  3. SystemVerilog-AXI4S-ImageVerify SystemVerilog-AXI4S-ImageVerify Public

    SystemVerilog

  4. KNU-IDEC-Contest-2024_CNN_accelerator KNU-IDEC-Contest-2024_CNN_accelerator Public

    This project was conducted as part of the IDEC 2024 Creative Circuit Design Challenge at Kyungpook National University. We designed a Convolutional Neural Network (CNN) for MNIST handwritten digit …

    Verilog 1

  5. DIgital_System_Design_MLP_MNIST DIgital_System_Design_MLP_MNIST Public

    This project was undertaken as part of the Digital System Design course at Seoul National University of Science and Technology. The goal was to implement a Multi-Layer Perceptron (MLP) model provid…

    VHDL

  6. SPI_Oled SPI_Oled Public

    This project implements a reaction time game using the FPGA Z7-20 development board, featuring a custom SPI-controlled OLED display and a ZYNQ Processing System (PS). The game challenges users to q…

    VHDL