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Memif address range fix #252

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Merged
aolofsson merged 2 commits into from
Jan 26, 2026
Merged

Memif address range fix #252

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7b79b00
Extending lambdalib range
aolofsson Jan 26, 2026
ac2f245
Fixing memory addres bug
aolofsson Jan 26, 2026
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2 changes: 1 addition & 1 deletion pyproject.toml
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Original file line number Diff line number Diff line change
Expand Up @@ -19,7 +19,7 @@ requires-python = ">= 3.9"
license = {file = "LICENSE"}
dependencies = [
"siliconcompiler >= 0.35.0",
"lambdalib >= 0.4.0, < 0.9.0"
"lambdalib >= 0.4.0, < 0.10.0"
]
dynamic = ["version"]

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39 changes: 19 additions & 20 deletions umi/sumi/umi_memif/rtl/umi_memif.v
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Expand Up @@ -17,30 +17,29 @@

module umi_memif
#(parameter DW = 256, // umi packet width
parameter AW = 64, // umi address width
parameter MAW = 32 // ram address width
parameter AW = 64 // umi address width
)
(// ctrls
input clk,
input nreset,
input clk,
input nreset,
// umi interface
input umi_read, // memory read
input umi_write, // memory write
input umi_atomic, // read-modify-write
input [2:0] umi_size, // 1 --> DW/8 byte
input [7:0] umi_len, // total transfers = LEN + 1
input [7:0] umi_atype, // atomic type
input [AW-1:0] umi_addr, // size aligned address
input [DW-1:0] umi_wrdata,
output [DW-1:0] umi_rddata,
output umi_ready,
input umi_read, // memory read
input umi_write, // memory write
input umi_atomic, // read-modify-write
input [2:0] umi_size, // 1 --> DW/8 byte
input [7:0] umi_len, // total transfers = LEN + 1
input [7:0] umi_atype, // atomic type
input [AW-1:0] umi_addr, // size aligned address
input [DW-1:0] umi_wrdata,
output [DW-1:0] umi_rddata,
output umi_ready,
// mem interface
output mem_ce,
output mem_we,
output [MAW-1:0] mem_addr,
output [DW-1:0] mem_wrmask,
output [DW-1:0] mem_wrdata,
input [DW-1:0] mem_rddata
output mem_ce,
output mem_we,
output [AW-1:0] mem_addr,
output [DW-1:0] mem_wrmask,
output [DW-1:0] mem_wrdata,
input [DW-1:0] mem_rddata
);

// local state
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