Adding a Verilog example using PicoSoC #39

gatecat · 2025-05-14T07:16:20Z

Everything else is ready for review, although I have a couple of questions:

should this be in this repo at all, or a different one?
should the top level wrapper still use amaranth-orchard pin signatures, as it does now, or is it clearer if it defines the pin signatures in the wrapper too (e.g. as an example for people who want to wrap Verilog with other types of IO)

robtaylor · 2025-05-14T10:14:08Z

I think it belongs here. Defining the iopins here is better as well.

Let's not add a makefile - it was removed from the others.
Trying to keep things as windows compatible as we can, though still need to test.

gatecat · 2025-05-14T14:42:00Z

Let's not add a makefile - it was removed from the others.

Seems like it wasn't? e.g. https://github.com/ChipFlow/chipflow-examples/blob/main/mcu_soc/Makefile

gatecat · 2025-07-14T08:21:27Z

Hopefully once ChipFlow/chipflow-lib#129 is in this is ready to go!

robtaylor · 2025-07-14T12:19:36Z

picosoc_verilog/design/design.py

+        base = os.path.dirname(__file__)
+
+        verilog_sources = [
+            f"{base}/picosoc_asic_top.v",
+            f"{base}/picorv32/picosoc/spimemio.v",
+            f"{base}/picorv32/picosoc/simpleuart.v",
+            f"{base}/picorv32/picosoc/picosoc.v",
+            f"{base}/picorv32/picorv32.v",
+        ]
+
+        for verilog_file in verilog_sources:
+            with open(verilog_file, 'r') as f:
+                platform.add_file(verilog_file, f)
+


Just wondering, could we have a chipflow.toml section to include external code, or maybe use a seperate toml file for defining the import?

any progress on this?

robtaylor · 2025-07-14T12:24:34Z

picosoc_verilog/design/design.py

+            # Clock and reset
+            i_clk=ClockSignal(),
+            i_resetn=~ResetSignal(),
+
+            # UART
+            o_ser_tx=self.uart_0.tx.o,
+            i_ser_rx=self.uart_0.rx.i,
+
+            # SPI flash
+            o_flash_csb=self.flash.csn.o,
+            o_flash_clk=self.flash.clk.o,
+
+            o_flash_io0_oe=self.flash.d.oe[0],
+            o_flash_io1_oe=self.flash.d.oe[1],
+            o_flash_io2_oe=self.flash.d.oe[2],
+            o_flash_io3_oe=self.flash.d.oe[3],
+
+            o_flash_io0_do=self.flash.d.o[0],
+            o_flash_io1_do=self.flash.d.o[1],
+            o_flash_io2_do=self.flash.d.o[2],
+            o_flash_io3_do=self.flash.d.o[3],
+
+            i_flash_io0_di=self.flash.d.i[0],
+            i_flash_io1_di=self.flash.d.i[1],
+            i_flash_io2_di=self.flash.d.i[2],
+            i_flash_io3_di=self.flash.d.i[3],
+
+            # LEDs
+            o_leds=self.gpio_0.gpio.o


Again, might be something worth putting in a toml description?

gatecat · 2025-09-16T07:25:33Z

@robtaylor as "proper" Verilog support has turned into a bigger project, shall we at least get this merged in its current form (I've rebased and updated it, I don't think any of the other PRs should affect it) so we have some kind of Verilog example to point to?

robtaylor · 2025-09-16T17:19:16Z

@robtaylor as "proper" Verilog support has turned into a bigger project, shall we at least get this merged in its current form (I've rebased and updated it, I don't think any of the other PRs should affect it) so we have some kind of Verilog example to point to?

Yes @gatecat , sounds sensible to me. Can you rebase now software-rework has landed?

Signed-off-by: gatecat <gatecat@ds0.me>

gatecat · 2025-09-29T12:46:07Z

Rebasing ended up a bit more complex than expected, but with ChipFlow/chipflow-lib#143, I think this should now be working

robtaylor · 2025-10-10T11:24:46Z

picosoc_verilog/design/software/doit_build.py

don't think this should be necessary now?

if the chipflow-lib impl doesnt do something you need, lets fix that

It would be a ton of work to get software building working with Verilog, and I don't think everyone is even going to want this

fair enough, see other comment..

robtaylor · 2025-10-10T11:27:21Z

picosoc_verilog/design/software/main.c

Should the flashio/cmd_read_*/set_flash parts here be in the QSPIFlash driver?
Maybe fix up chipflow-lib if drivers need a way to put stuff in start.S?

The picosoc qspi flash core isn't compatible with the one in chipflow-digital-ip so different drivers is needed

ah, i see. this is fine for now then i guess, as you're overriding software build. We should have a bit of a session on making sure we can have design specific drivers work alongside imported drivers.

robtaylor · 2025-10-10T11:31:32Z

picosoc_verilog/design/software/main.c

+}
+
+void print_dec(uint32_t v)
+{


Why not something like:
do // run at least once to print 0
{
d = x % 10;
stack[sp++] = d + '0'; // push
x /= 10;
} while (x);

?

I don't know, this was just taken from claire's picosoc code as-is

how odd... Maybe note its origin in a comment?

robtaylor · 2025-10-10T11:33:20Z

picosoc_verilog/design/design.py

+        base = os.path.dirname(__file__)
+
+        verilog_sources = [
+            f"{base}/picosoc_asic_top.v",
+            f"{base}/picorv32/picosoc/spimemio.v",
+            f"{base}/picorv32/picosoc/simpleuart.v",
+            f"{base}/picorv32/picosoc/picosoc.v",
+            f"{base}/picorv32/picorv32.v",
+        ]
+
+        for verilog_file in verilog_sources:
+            with open(verilog_file, 'r') as f:
+                platform.add_file(verilog_file, f)
+


any progress on this?

robtaylor · 2025-10-16T19:06:30Z

Also seems this is using the long-deprecated PinSignature?? Please check you're working against a current chipflow-lib

gatecat · 2025-10-16T19:13:34Z

Hm, where is that, I thought I moved to using all the predefined signatures in chipflow-lib so sim auto-generation works, but maybe some old code got left in by mistake...

gatecat · 2025-10-16T19:18:30Z

I also don't touch pyproject.toml or pdm.lock in this PR so CI (where the tests pass, only the known issue of minimal timing out in the cloud builder causes a failure) should be using latest chipflow-lib already

robtaylor · 2025-10-16T19:23:45Z

Maybe my local branch got messed up somehow, let me check it!

gatecat requested a review from robtaylor May 14, 2025 07:16

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Adding a Verilog example using PicoSoC

8086479

Signed-off-by: gatecat <gatecat@ds0.me>

gatecat force-pushed the add-verilog-example branch from 9a82105 to 8086479 Compare September 29, 2025 12:45

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Adding a Verilog example using PicoSoC #39

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