Add refs through interpshinx #1
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Similarly to VHDL/pyVHDLModel/pull/32, this PR is a draft for showing an issue I'm finding when trying to use intersphinx for cross-referencing labels in pyVHDLModel and pySystemVerilogModel.
It is particularly surprising to me that refs to
python:comparisonsand/orOSVB:API:Coreare correct, but others fail.