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Add refs through interpshinx #1

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129465f
TEST intersphinx
umarcor Sep 26, 2021
b90167d
TEST lowercase intersphinx ids
umarcor Oct 2, 2021
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18 changes: 17 additions & 1 deletion ConceptualModel.rst
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Expand Up @@ -41,7 +41,23 @@ Its goal is the interoperability of diverse tools and languages with documented

3 | Language Model
Syntax/design Document Object Model (DOM) of the language(s).
See :doc:`vhdlmodel:index`, :doc:`svmodel:index` and :ref:`OSVB: pyVHDLModelUtils <OSVB:API:Project:pyVHDLModelUtils>`.

* ``ref | goals`` :ref:`goals`
* ``ref | pyVHDLModel:goals`` :ref:`pyVHDLModel:goals`
* ``ref | pyvhdlmodel:goals`` :ref:`pyvhdlmodel:goals`

* ``doc | Glossary`` :doc:`Glossary`
* ``doc | pyVHDLModel:Glossary`` :doc:`pyVHDLModel:Glossary`
* ``doc | pyvhdlmodel:Glossary`` :doc:`pyvhdlmodel:Glossary`

* ``ref | vhdlmodel`` :ref:`vhdlmodel`
* ``ref | pyVHDLModel:vhdlmodel`` :ref:`pyVHDLModel:vhdlmodel`
* ``ref | pyvhdlmodel:vhdlmodel`` :ref:`pyvhdlmodel:vhdlmodel`

* ``doc | pySVModel:Glossary`` :doc:`pySVModel:Glossary`
* ``ref | pySVModel:svmodel`` :ref:`pySVModel:svmodel`

See :doc:`pyVHDLModel:index`, :doc:`pySVModel:index` and :ref:`OSVB: pyVHDLModelUtils <OSVB:API:Project:pyVHDLModelUtils>`.

4 | Project
Tool independent information (files/filesets, primary design units, testbenches, `hdl/constraints <https://github.com/hdl/constraints>`__,
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4 changes: 2 additions & 2 deletions conf.py
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Expand Up @@ -178,8 +178,8 @@ def _LatestTagName():
intersphinx_mapping = {
'python': ('https://docs.python.org/3', None),
'osvb': ('https://umarcor.github.io/osvb', None),
'vhdlmodel': ('https://vhdl.github.io/pyVHDLModel', None),
'svmodel': ('https://edaa-org.github.io/pySystemVerilogModel', None),
'pyvhdlmodel': ('https://vhdl.github.io/pyVHDLModel', None),
'pysvmodel': ('https://edaa-org.github.io/pySystemVerilogModel', None),
}


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