Renamed variable sequence, as sequence is a reserved word in VHDL-2008
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Renamed variabel `sequence` to `seq` as `sequence` is a reserved word from IEEE Std 1076-2008 onwards (see IEEE Standard VHDL Language Reference Manual, section 15.10 Reserved words).
…lity Update strings_maps.vhdl
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Renamed variable
sequencetoseqassequenceis a reserved word from IEEE Std 1076-2008 onwards (see IEEE Standard VHDL Language Reference Manual, section 15.10 Reserved words).