QCLINUX: arm64: dts: qcom: x1e80100: Add dma-ranges to support 40 bit… #394
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…bug block Add below Coresight devices for APSS debug block: -ETM -TMC ETF -Funnel -Replicator Link: https://lore.kernel.org/all/20251027-cpu_cluster_component_pm-v1-12-31355ac588c2@oss.qualcomm.com/ Signed-off-by: Yuanfang Zhang <yuanfang.zhang@oss.qualcomm.com> Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
Previously, the eDP panel backlight was enabled via UEFI. Added backlight control node in kernel DTS due to some meta may not enable the backlight. Aligned with other x1e80100-based platforms: the PWM signal is controlled by PMK8550, and the backlight enable signal is handled by PMC8380. Link: https://lore.kernel.org/all/20251028-hamoa_dvt_backlight-v1-1-97ecb8d0ad01@oss.qualcomm.com/ Signed-off-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com>
Embedded Trace Router(ETR) is working as a DDR memory sink to collect tracing data from source device. The CTCU serves as the control unit for the ETR device, managing its behavior to determine how trace data is collected. Link: https://lore.kernel.org/all/20251104-enable-etr-and-ctcu-for-hamoa-v1-2-af552cfb902c@oss.qualcomm.com/ Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
…PI11 access GPIOs 44-47 were previously reserved, preventing Linux from accessing SPI11 (qupv1_se3). Since there is no TZ use case for these pins on Linux, they can be safely unreserved. Removing them from the reserved list resolves the SPI11 access issue for Linux. Link: https://lore.kernel.org/linux-arm-msm/20251106102448.3585332-1-xueyao.an@oss.qualcomm.com/ Signed-off-by: Xueyao An <xueyao.an@oss.qualcomm.com>
Enable ST33HTPM TPM over SPI11 on the Hamoa IoT EVK by adding the required SPI and TPM nodes. Link: https://lore.kernel.org/all/20251112-arm64-dts-qcom-hamoa-iot-evk-enable-st33-tpm-on-spi11-v3-1-39b19eb55cc3@oss.qualcomm.com/ Signed-off-by: Khalid Faisal Ansari <khalid.ansari@oss.qualcomm.com>
…-SOM platform HAMOA IoT SOM requires PCIe3 and PCIe5 connectivity for SATA controller and SDX65. Add the required sideband signals (PERST#, WAKE#, CLKREQ#), pinctrl states and power supply properties in the device tree, which PCIe3 and PCIe5 require. Link: https://lore.kernel.org/all/20251112090316.936187-2-ziyue.zhang@oss.qualcomm.com/ Signed-off-by: Ziyue Zhang <ziyue.zhang@oss.qualcomm.com> Reviewed-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
…IOT-EVK board HAMAO IoT EVK uses PCIe5 to connect an SDX65 module for WWAN functionality and PCIe3 to connect a SATA controller. These interfaces require multiple voltage rails: PCIe5 needs 3.3V supplied by vreg_wwan, while PCIe3 requires 12V, 3.3V, and 3.3V AUX rails, controlled via PMIC GPIOs. Add the required fixed regulators with related pin configuration, and connect them to the PCIe3 and PCIe5 ports to ensure proper power for the SDX65 module and SATA controller. Link: https://lore.kernel.org/all/20251112090316.936187-3-ziyue.zhang@oss.qualcomm.com/ Signed-off-by: Ziyue Zhang <ziyue.zhang@oss.qualcomm.com> Reviewed-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
… address for NVMe The current dma-ranges configuration limits DMA addressing to 36-bit, but Hamoa's memory can extend up to 40-bit addresses. This mismatch causes issues when the NVMe driver allocates buffers beyond the 36-bit boundary, triggering swiotlb bounce operations. During bounce operations, the dma_skip_sync flag (initially set to true due to dma-coherent property) gets reset to false, causing the NVMe driver to access unallocated buffers pointed by iod->dma_vecs. Fix this by updating the PCIe RC dts node dma-ranges to support full 40-bit addressing, eliminating the need for swiotlb bounce operations and preventing the dma_skip_sync flag corruption. Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
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Dec 8, 2025
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QCLINUX: arm64: dts: qcom: x1e80100: Add dma-ranges to support 40 bit address for NVMe
Downstream patches are not allowed on qli mainline. Please submit it upstream
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… address for NVMe
The current dma-ranges configuration limits DMA addressing to 36-bit, but Hamoa's memory can extend up to 40-bit addresses. This mismatch causes issues when the NVMe driver allocates buffers beyond the 36-bit boundary, triggering swiotlb bounce operations.
During bounce operations, the dma_skip_sync flag (initially set to true due to dma-coherent property) gets reset to false, causing the NVMe driver to access unallocated buffers pointed by iod->dma_vecs.
Fix this by updating the PCIe RC dts node dma-ranges to support full 40-bit addressing, eliminating the need for swiotlb bounce operations and preventing the dma_skip_sync flag corruption.